Flash memory devices such as those used in solid-state disks require error correcting codes in order to prevent information loss. Bit error rates in such memory devices are increasing with each new device generation as semiconductor feature sizes are reduced and the number of bits per memory cell is increased. The result is a need for different error correction capabilities in different flash memory controllers and different amounts of reserved semiconductor area for parity bits in successive device generations.
In a flash memory device such as a NAND gate-based memory device, data is generally stored in blocks of, e.g., 512 bytes, i.e., in blocks of 4096 bits. Parity bits are added to each block of data so that a number of bit errors can be detected and corrected. For a block of 512 bytes, 78 parity bits can be added to the 512 bytes to provide error detection and correction capability for up to six bits.
Hardware solutions with programmable error correction capability using Reed-Solomon codes have been used for various error detection and correction applications, e.g., magnetic memory devices such as hard disk drives which generally produce bursts of errors. However, these are not well suited for flash memory devices which suffer from isolated random errors. A BCH code is the preferred protection technique for the random errors encountered in flash memory devices.
A substantial amount of logic and associated semiconductor area must be included in a flash memory controller to provide a high level of encoding and decoding capability such as to correct six bits or more in a block of 512 bytes. It is now common practice to provide a specific design for a flash memory controller to detect and correct a particular number of error bits.
A BCH encoder and decoder employing conventional design practices would switch between different BCH encoder implementations to provide different levels of error detection and correction capability, wasting semiconductor area and limiting programmability to the particular BCH encoders included in the design. In order to provide a common controller that can be used for different flash memory devices, a BCH encoder with programmable error correction capability would provide an advantageous solution, substantially reducing the semiconductor area required for the long BCH block codes used in flash memory devices.